发明名称 PULSE GENERATING CIRCUIT
摘要 PURPOSE:To obtain pulse outputs of fixed time width by continuing output of specified state of a flip-flop for a period determined by a specific number of clock pulses that passed an inhibit circuit. CONSTITUTION:Clock pulse are inputted to a counter 12 through an inhibit circuit 11 and output 13 of the counter 12 is inputted to the reset terminal of an RS type flip-flop 15. Output 16 of the flip-flop 15 is outputted as output pulse of the circuit, and at the same time, acts as a control signal 16a of an inhibit circuit 13. When output 16 of the flip-flop 15 is 'H', the inhibit circuit 11 passes the clock pulse, and checks when the output is 'L'. As the period in which output 16 is 'H' corresponds to a period in which specified number of clock pulses are inputted, the time can be determined exactly.
申请公布号 JPS61140215(A) 申请公布日期 1986.06.27
申请号 JP19840262001 申请日期 1984.12.12
申请人 NEC CORP 发明人 KASAI MACHIROU
分类号 H03K5/05;H03K5/04 主分类号 H03K5/05
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