| 摘要 |
<p>PURPOSE:To improve the compressing rate by generating a representing flag at each block through the discrimination of majority decision logic without giving a flat to each of interpolation point and transmitting the representive flag in place of plural interpolation points in the block. CONSTITUTION:Picture element data of an interpolation point D is outputted as an output of a sample delay circuit 9 to form a flag relating to the interpolation point D. Picture element data at a sub-sample point (a) from a sample delay circuit 14 and picture element data at a sub-sample point (h) from an input terminal 1 are fed to and adder 15. Outputs 11-14 of adders 15, 18 are interpolation data in longitudinal, lateral and oblique directions, in total 4 directions with respect to the interpolation point D. A flag generating circuit 19 operates an absolute value being a difference between the true value and each of interpolation data 11-14 of the picture element data of the flag D from the sample delay circuit 9 to generate a flag in 2-bit representing the direction of the interpolation minimizing the value. The flag for 8 interpolation points is fed to a majority decision logic circuit 31 and a flag having the largest number is selected.</p> |
