发明名称 MUTING CIRCUIT
摘要 PURPOSE:To eliminate a potential difference between the DC potential and the clamp potential of an output at the time of muting and in a usual video signal period, by fixing a sample and holding circuit to a sample state and controlling an output voltage, at the time of muting. CONSTITUTION:In a state that no mute signal exists, an output of an outputting circuit 6 is compared with a reference voltage from a reference potential source 11 by a comparator 12, and provided to a sample and holding circuit 13. In the circuit 13, by a gate pulse applied to a terminal 15, a comparison voltage is sampled to a capacitor 18 in a gate pulse period, holding is executed in other period, and by controlling a variable DC shifting circuit 10 by this holding voltage, an outputted video signal is clamped. On the other hand, when a mute signal has been impressed to a mute signal input terminal 5, the potential from a DC potential source 8 passes through the circuit and appears in an output terminal 7. In this case, at the time of muting, the circuit 13 is fixed to a holding state, and the potential from the reference potential source 11 is outputted to the terminal 7.
申请公布号 JPS61139904(A) 申请公布日期 1986.06.27
申请号 JP19840262009 申请日期 1984.12.12
申请人 NEC CORP 发明人 AMANO TATSUYUKI
分类号 G11B20/02;G11B5/027;(IPC1-7):G11B5/027 主分类号 G11B20/02
代理机构 代理人
主权项
地址