发明名称 SILICON ETCHING METHOD
摘要 PURPOSE:To stably promote the passivation for the positive electrode side by directly applying the voltage between the juncted p-layer and the n-layer. CONSTITUTION:The n-layer is used for positive electrode and the p-layer is used for the negative electrode in the p-n junction silicon wafer so that the negative electrode current flowing into the alkaline solution is restricted only to the n-layer, with the result that the current does not flow from the p-layer. Since the passivation layer is formed only by the positive electrode current, it is made possible to stably promote the passivation on the n-layer part as a positive electrode, thereby permitting the etching in a stabilized state.
申请公布号 JPS61139031(A) 申请公布日期 1986.06.26
申请号 JP19840261466 申请日期 1984.12.11
申请人 YOKOGAWA ELECTRIC CORP 发明人 IKEDA KYOICHI;ISOZAKI KATSUMI;WATANABE TETSUYA
分类号 H01L21/3063;H01L21/306;(IPC1-7):H01L21/306 主分类号 H01L21/3063
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