| 摘要 |
PURPOSE:To improve the degree of integration to make the circuit scale small in size by supplying the inter-stage tap output of the first and the second delay circuits and that from the second terminal to the first adder to add them and multiplying the output of the first adder by a filter coefficient and accumulating the result to the filter operation output of another tap output. CONSTITUTION:Registers 1 and 2 are connected in series, and a terminal P1 is led out from one end of the register 1, and a terminal P2 is led out from one end of the register 2. The connection point of registers 1 and 2 is connected to one input terminal of an adder 4, and a terminal P3 is led out from the other input terminal of the adder 4. The output terminal of the adder 4 is connected to one input terminal of a multiplier 6. A terminal P4 is led out from the other input terminal of the multiplier 6. The output terminal of the multiplier 6 is connected to one input terminal of an adder 5. a terminal P5 is led out from the other input terminal of the adder 5. The output terminal of the adder 5 is connected to one end of a register 3. a terminal P6 is led out from the other end of the register 3. These registers 1, 2, and 3, adders 4 and 5, and multiplier 6 are arranged on the same integrated substrate. |
