| 摘要 |
PURPOSE:To set up a brake point also at an optional address and to attain also the debugging of a ROM software by storing the information of the brake point in a memory different from a main memory. CONSTITUTION:If a certain address in a main mory unit 2 when a processor unit (PU) 1 executes a program, the same address in a brake point memory (BPM) 4 is simultaneously read out. If an output 161 or 162 in a BPM signal 16 of the BPM4 is active, the setting of the brake point in the address is indicated. When the brake conditions of the outputs 161, 162 indicating that the memory access is a memory read or a memory write respectively coincide with each other, an interruption request signal 17 is made active. When an interruption is requested to the PU1, the program in executing is interrupted and a brake point processing routine is started. |
