| 摘要 |
PURPOSE:To make using efficiency of an address line and a data bus 100% by repeating the continuous output of one writing instruction and one reading inctruction. CONSTITUTION:When a 0 WAY (even No.) is selected by an WAY address, a signal SEL 00 WAY is outputted. Consequently, a clock CLK is applied only to WD REG 0 WAY in a data register 10 and data on a store data bus are stored. At that time the output SEL 00 WAY of the data 9 is set up to SEL 00 REG and inputted to a multiplexer MPX 01 with 1tau delay. Since the MPX 01 is controlled so as to select the output of the SEL 00 REG at the select signal output timing of the ODD WAY by a control signal SEL 16B at the 16-byte access operation, the MPX 01 impresses a CLK delayed by 1tau from the CLK to the WD REG 1 WAY of the register 10. At that time the 2nd 8-byte data on the store data bus are stored in the WD REG 1 WAY.
|
