发明名称 COMMAND RETRIAL SYSTEM
摘要 PURPOSE:To reduce the load applied to the programs of a host processor and a processor part by providing a memory at a channel control part to store the buffer information and performing a command retrial based on the stored information in an overrun or underrun mode. CONSTITUTION:A memory GBKB 6 stores the obtained buffer information; while a memory ICBW 7 stores the IWC which is reported to a PC. Both memories 6 and 7 work while a command is executed respectively. thus the command retrial is attained without applying the load at all to the programs of a host processor and a CCP in case an overrun or an underrun is produced. Furthermore the overall processing capacity is improved for an information processing system. While no processing is applied to the reported ICW until the ICW (normal end, error end, etc.) of the end information is delivered in agreement with the program of the CCP. As a result, the same function is attained with no use of both memories ICWBC 7 and ICWBC 9.
申请公布号 JPS61136153(A) 申请公布日期 1986.06.24
申请号 JP19840258592 申请日期 1984.12.07
申请人 FUJITSU LTD;NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SHIBATA HIROKI;TONE FUJIMITSU
分类号 G06F13/12;(IPC1-7):G06F13/12 主分类号 G06F13/12
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