| 摘要 |
PURPOSE:To attain the frequency multiplication with a small time delay by counting the input signals with a 1/m-divided reference signal and then subtracting the count value of the input signals by a 1/i-divided reference signal. CONSTITUTION:A frequency divider 4 1/m-divides the reference signal of an oscillator 6 and supplies the divided signal to a counter 1 as a clock (e). In the same way, a frequency divider 5 1/i-divides said reference signal and supplies it to a counter 3 as a clock (f). Then the control 1 counts the input signals (a) with the clock (e) and this count value is stored to a latch 2. While the counter 3 subtracts the count value stored by the latch 2 by the clock (f) as the register number and delivers a borrow number signal. This operation is repeated for output of the frequency multiplication output (d). Thus the multiplied output of a magnification ratio m/i is obtained. In such a way, the frequency multiplication is possible with a small time delay.
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