发明名称 PHASE LOCKED LOOP OSCILLATOR
摘要 PURPOSE:To obtain a highly stable PLL oscillation circuit with cost reduction by having the comparison of phase between the frequency obtained by shifting down the oscillation frequency of a VCO and the divided frequency of the output of a reference oscillator and controlling the VCO with the comparison output. CONSTITUTION:The output of a reference oscillator 15 is partly multiplied by a harmonic generator 16 and applied to a mixer 14 together with the output of a VCO1. Then the output of a difference frequency is extracted and divided by a frequency divider 17 to be applied to a phase comparator 4. Another part of the output of the oscillator 15 is divided by a frequency divider 18 and applied to the comparator 4 to receive the comparison of phase with the output of the divider 17. Then the voltage corresponding to a phase difference is extracted. This voltage controls the oscillation frequency of the VCO1 through a loop filter 5 to always keep the phase difference at zero. Thus a divider for microwave band is not needed for a PLL oscillation circuit for microwave band. This attains the cost reduction of a PLL oscillator.
申请公布号 JPS61135227(A) 申请公布日期 1986.06.23
申请号 JP19840256996 申请日期 1984.12.05
申请人 FUJITSU LTD 发明人 UEDA HIROKAZU;NISHIDA HARUKI
分类号 H03L7/18;H03L7/06 主分类号 H03L7/18
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