CMI CODE ERROR DETECTING CIRCUIT

摘要

PURPOSE:To attain the assured detection of an error of the CMI signal by using two error detecting circuits after holding the word bit levels of the first and second halves of the CMI signal by different holding circuits and then converting these levels into NRZ signals. CONSTITUTION:The word bits of the first and second halves of an input CMI signal are held by holding circuits 10 and 11 respectively. Then signals A and B are delivered with synchronization secured between both signals and then supplied to a logical circuit 12 and error detecting circuits 13 and 14 respectively. The circuit 12 delivers an NRZ signal which is set at 1 when the coincidence is obtained between both signals A and B and otherwise set at 0. The circuit 13 delivers a signal H when 0 of the signal A and 1 of the signal B are detected. The circuit 14 delivers a signal I when the coincidence of level is secured among signals A and B and the output signal M of a 1/2 dividing circuit 19. The OR output of signals G and H and the signal I are supplied to logical circuits 16 and 17. These circuits 16 and 17 deliver pulse signals J and K for each cycle of a clock and supplies the OR output of both signals to the circuit 19. While the OR output of signals H and I undergoes the waveform shaping through a logical circuit 21 with the signal M given from the circuit 19. Then an error detecting signal is delivered.