| 摘要 |
PURPOSE:To remarkably improve an average data transferring speed in which -RAS cycle is considered by repeating -CAS cycle with a desired number of times within one time of -RAS cycle as for all data stored in memory cells corresponding to one line address. CONSTITUTION:A signal -RAS descends and a lime address signal AiR is fetched into a line decoder 2. Then one line of memory cells is selected and the data of the memory cells are latched by a sense amplifier 4. Thereafter, a signal -CAS descends and a row address signal AiC is fetched into a row decoder 5 through a multiplexer 12. Then 4-bit data from the sense amplifier 4 are transferred to a 4-bit shift register 7 through a transfer gate circuit 13 and the one bit of the address designated by the row address signal AiC is trans ferred to an output buffer 8 and becomes output data Dout. When the signal -CAS ascends thereafter, the output of a 2-bit down counter 15 becomes ''H'' level and the row address signal A>=C is advanced step by step, and thus, a new internal row address signal (AiC+4) is obtained.
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