| 摘要 |
PURPOSE:To prevent the effects of short circuit and electric field between a wiring layer and source-drain regions by making the area except that of the FET element forming region as small as possible, by a method wherein an electrical connection aperture, i.e. contact hole is provided directly above the gate electrode and electrically connected with the wiring layer. CONSTITUTION:A source region 1 and a drain region 2 are formed in the process of impurity diffusion by a method such as ion implantation. In this case, the source region 1 and the drain region 2 are formed in self-alignment by an Si nitride film 24, an Si oxide film 23, a gate electrode 3, and an Si oxide film 21 that is the element-forming region. The region between both the diffused regions becomes a channel 28 under the gate electrode 3 and a gate oxide film 25 and serves as a constituent of the FET. Next, after annealing, selective oxidation is carried out by using the Si nitride film 24 on the gate electrode 3 as the mask, thus forming a thick Si oxide film 29 on the source region 1 and the drain region 2. Successively, the nitride film 24 and the oxide film 23 are removed, and an interlayer insulation film is formed by coating over the whole surface. |
