| 摘要 |
PURPOSE:To control a memory and an I/O device with a different CPU by switching plural CPUs with a reset signal to decrease the number of additional circuits. CONSTITUTION:A reset signal is given from a device 6 to a CPU 2 at the initial state, a control signal 15 for a data bus 8, an address bus 9 and the CPU 2 is in high impedance state and the data bus 8 and the address bus 9 are controlled by a CPU 1. When the processing of the CPU 1 is finished and it is required to operate the CPU 2, the CPU 1 accesses a reset switching circuit 7, which resets the CPU 1 to bring the output of the data bus 8 and the address bus 9 to a high impedance. The reset of the CPU 2 is released, the CPU 2 starts operation to actuate the data bus 8 and the address bus 9, and the control signal 15 is being supplied. When the processing of the CPU 2 is finished, the CPU 1 is switched by allowing the CPU 2 to access the reset switching signal 7 in the same way as the CPU 1. |
