| 摘要 |
PURPOSE:To attain high-speed invalidated processing of an address conversion buffer by providing an invalidated bit memory storing an effective bit of n bits per entry to n entries of the address conversion buffer memory. CONSTITUTION:Invalidated bits corresponding to n-entry's share of the address conversion buffer memory 10 are arranged in the column direction and an invalidated bit memory 11 made of N/n entries to the total entry number N of the address conversion buffer memory 10is provided. Thus, the n entries of the address conversion buffer memory is invalidated for one time. Thus, the invalidated processing time of the address conversion buffer memory is reduced to 1/n of a conventinal circuit.
|
