| 摘要 |
PURPOSE:To receive instantly a DMA request from an external device by providing a direct memory access means, a stop means intermitting data transfer between memories operated in response to the direct memory access request from an I/O device and a restart means. CONSTITUTION:When an L level signal is inputted from an AND gate 7 to terminals EOP and DREQ3 of a DMAC 4, the L level signal inputted to the terminal EOP interrupts immediately the data transfer. On the other hand, the L level signal inputted to the terminal DREQ3 allows the DMAC 4 to output a signal HLDREQ to request a CPU 1 to quit the bus, the CPU 1 floats an address data line in response to the said request and outputs a signal HLDACK to the DMAC 4. When the address data control line of a memory 3 is opened, the DMAC 4 transmits a proper address, a READ signal, a WRITE signal and a control signal to the memory 3 to transfer newly data between an I/O device and the memory 3. |
