| 摘要 |
PURPOSE:To reduce a chip area by advancing the disposition of a cell and the step of deciding the mutual wirings between cells relatively in a concerning manner when designing an LSI by a cell type layout to efficiently decide a chip size, thereby preventing a wasteful region from generating as small as possible. CONSTITUTION:The number of wirings 6 to be presumed to be superposed is counted in a range of y-coordinates in which call contained in i-th cell 2i from the bottom exists to obtain the width Wi in X-direction of wiring region 3 for wiring them, and if the total sum of the widths of the cells is Ci, the cell line 2k that Ci+Wi(Wi=WiR+WiL) becomes maximum is obtained. The cell line 2l that Ci+Wi becomes minimum is obtained, and the width D of the wasteful region =(Ck+Wk)-(Cl+Wl) is obtained. The cell line 2k is shifted to cell line 2l. The cell for movement is obtained by ¦D-P/2¦ is a certain value deltawhen the width of the cell to be noted is P, and the cell contained in the cell line 2 and the cell having wiring requests of the most number are obtained. This is removed from the cell line 2K, and inserted to between the cells for holding Y-coordinates of the cell line 2l. |
