| 摘要 |
PURPOSE:To obtain an analog output without distortion by using a clock signal phase-locked to a synchronizing signal detected from a digital input signal so as to demodulate, D/A-convert and sample-and-hold the input signal. CONSTITUTION:When a digital input signal RX is inputted to a detection circuit 2, a synchronizing signal 2FSR is detected. The synchronizing signal has a frequency twice the sampling frequency fS and fed to a phase comparator 3 of a phase locked loop PLL circuit 7 and compared with a feedback signal from a frequency divider 6, a phase comparison error signal is converted into a DC voltage by a loop filter 4, a clock signal RXCP is extracted from a control voltage oscillator 5 controlled by this voltage, and the signal RXCP is fed to a demodulation circuit 8 together with the signal RX. These signals are subjected to serial/parallel conversion 9 and D/A conversion 10 and then sample-and-hold 11, and an analog signal without distortion is outputted (15). |
