| 摘要 |
PURPOSE:To reduce the scale of the circuit by decoding a tri-state signal depending on the occurrence state of the length of the minimum unit of an O part of an input signal. CONSTITUTION:The AND of a signal by inverting the input signal with an NOT circuit 9 and an output of a 4D clock oscillator 7 are caught by an AND circuit 8 and the outputs is inputted to a clock terminal of a 4 bit counter 13. This 4 bit counter 13 is reset by the rising of the output of the NOT circuit 9 and length of the O level input signal is measured. The output of this 4 bit counter 13 logically processed by flip-flops 17-19, AND circuits 14-16, an output inversion exclusive OR circuit circuit 20 and when the minimum unit of the input signal O level length is expressed as 'L', and when in a 4 bit, 3L is continued twice, it is the first state signal and when 5L occurs once, it is the second state signal and otherwise, it is the 3rd state signal. |
