发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To reduce the base resistance by a method wherein, within an SST-1A process producing a vertical structure bipolar transistor, a base lead out electrode is composed of dual layers comprising polycrystalline silicon layers and silicide layers. CONSTITUTION:Polycrystalline silicon layers 20 (3,000Angstrom thick) containing no impurity are ion-implanted with N type impurity around 10<21>cm<-3>. Next photoresist masks 21 are formed on emitter and collector electrode region to remove the N type polycrystalline silicon layers 20 utilizing the masks 21. Firstly an oxide film 11 is removed to expose a P type polycrystalline silicon layer 9 (base lead out electrode). Secondly after removing the masks 21, the N type impurity is activated by heat-treatment to be diffused to lower region forming an emitter region 22. Next the surface of N type polycrystalline silicon layers 20 and P type polycrystalline silicon layer 9 are converted into silicide layer 23. Finally aluminium films are patterned on electrode forming regions to form a collector electrode 24, a base electrode 25 and an emitter electrode 26.
申请公布号 JPS61131562(A) 申请公布日期 1986.06.19
申请号 JP19840252916 申请日期 1984.11.30
申请人 FUJITSU LTD 发明人 GOTO HIROSHI
分类号 H01L29/73;H01L21/28;H01L21/331;H01L29/45;H01L29/732 主分类号 H01L29/73
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