发明名称 GPIB CONTROL CIRCUIT
摘要 PURPOSE:To improve a DMA transfer efficiency by using effectively a counter to count he number of data transfer bytes when a direct memory access (DMA) is transferred and setting a special FF. CONSTITUTION:When a listener on an international measuring instrument standard interface bus GPIB is in the receiving condition, a DMA request signal is outputted from a BPIB controller LSI 3. Thus, the data read from a memory 2 are transferred to the controller LSI 3, an address counter 11 is incremented and a transfer byte number counter 12 is decremented. When the final data are transferred, a counting output value TC of a high level showing the final transfer byte is outputted from a counter 12 and an FF20 is set. Thus, even when the command is not given to a controller LSI 3 from a microcomputer 1, an EOI can be automatically sent to a control line of GPIB and a DMA transfer efficiency can be improved.
申请公布号 JPS61131155(A) 申请公布日期 1986.06.18
申请号 JP19840253022 申请日期 1984.11.30
申请人 TOSHIBA CORP 发明人 MAESUMI JUICHI
分类号 G06F13/28 主分类号 G06F13/28
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