发明名称 LRU MECHANISM
摘要 PURPOSE:To prevent execution of unnecessary page-in/out by outputting a page of page-out to a CPU when a minimum value of a level in search from a page table. CONSTITUTION:A timer process read modify write circuit 5, when a revised bit is logical 1, decreased a reference inputted from an LRU data bus, that is, a level and outputs logical 0 when level is logical 0 to the LRU data bus via a buffer circuit 8. The output data is rewritten into a data inputting the reference value of the page table 3. Since the counter 13 is incremented, the level is changed at the same time sequentially until a carry C from the counter 13 is fed to a reset terminal of a read/write control circuit 9, resulting that the reference value of all pages of the page table 3 is decreased by 1 level.
申请公布号 JPS61131143(A) 申请公布日期 1986.06.18
申请号 JP19840253189 申请日期 1984.11.30
申请人 CASIO COMPUT CO LTD 发明人 KANEMURA TOSHIAKI;SASAKI ISAO
分类号 G06F12/12 主分类号 G06F12/12
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