| 摘要 |
PURPOSE:To improve the arithmetic speed of a CPU, by comparing the coincidence between a write address and read address and executing a read instruction. CONSTITUTION:Firstly, after the write address of a write instruction to a cache memory 2 is written in a write address buffer 10 at a timing (a) by means of a controller 14 in stage C, the read address of a read instruction R to the cache memory 2 produced in the next place is compared with the write address stored in the buffer 10 by means of a comparator 11 at another timing (b). When the compared result does not coincide with each other, the write instruction W and read instruction R are executed in stages D, E, and W. When they coincide with each other, the read instruction R is executed after waiting three machine cycles after the write instruction W is executed, but, since both the addresses hardly coincide with each other, the arithmetic speed consequently becomes faster.
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