发明名称 |
LIMIT CHECKER FOR DIGITAL SINGLE CHIP INTEGRATED CIRCUIT |
摘要 |
A bounds checker consisting of a pair of comparators that each compare a 16-bit number with a lower and an upper limit stored in registers. The device is preferably constructed as a single integrated circuit chip employing emitter coupled logic (ECL) circuitry and can be made externally compatible with either transistor transistor logic (TTL) circuitry or ECL circuitry. The device can be cascaded to operate on extended-precision numbers and has a pin which can be used to select comparison of numbers either as signed two's complement numbers or as unsigned numbers. No added gate delay is imposed by the device's ability to operate either type of number. |
申请公布号 |
JPS61131036(A) |
申请公布日期 |
1986.06.18 |
申请号 |
JP19850269209 |
申请日期 |
1985.11.28 |
申请人 |
ADVANCED MICRO DEVICDS INC |
发明人 |
OORII EICHI MOORAA |
分类号 |
G06F7/38;G06F7/02;G06F7/508 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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