| 摘要 |
PURPOSE:To simplify the unit and to attain high speed processing by expanding processing data length for a rounding adder/subtractor and applying in advance arithmetic operation including digits expanded by a carry so as to eliminate the need for various circuits. CONSTITUTION:The processing data length of the rounding adder/subtractor 31 is expanded toward the lower-order by 2 digits so as to add the most significant bit of a preceding digit to the corresponding digit to any of the least significant bits in three digits of the low-order in response to the state of a mantissa part adding/subtracting adder/subtractor 18. Thus, the rounded data is outputted from the least significant bit, then neither a shifter nor an exponent switch selector is required. Further, the processing data length of an adder/ subtractor 31 is expanded by 1 bit toward the high-order and the arithmetic operation is executed in advance including digits expanded by the carry. Thus, generation of carry at rounding is prevented, the right shift function of a mantissa normalizing shifter is not required and a control circuit controlling the said shifter is not required. |
