| 摘要 |
A timing synchronization circuit for use in a multi-station communication system in which one station is a master station. The timing synchronization circuit within each station comprises a clock operating at a frequency nearly constant between the stations. The clock signal is frequency-divided to provide synchronization of the frames and blocks of the data being transmitted. The clock signal is reinitialized by a reset signal generated when a packet of data transmitted by the master station is received and recognized by the station by identifying code within the packet. The reinitialization accounts for the propagation delays relative to the master station.
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