发明名称 DATA TRANSFER SYSTEM
摘要 PURPOSE:To reduce the number of driver circuits in an I/O device by forming plural channels for counting up addresses in a memory and outputting a channel specifying signal at the transfer of data. CONSTITUTION:A CPU sets up a leading address in a counter having a presetting function and then sets up a channel No. of a memory to be used in a channel register of a register part 41' of an I/O control device 4. Obtaining a bus using right, the control part 41' outputs a channel address signal and a control signal. The memory discriminates these signals, validates an address gate signal corresponding to the channel concerned and reads out and outputs the data to a bus 3. The control part 41' enters the data on the bus 3 into a register part 42', transfers the data to an I/O device 5 and counts down the number of transfer words in a command register of the register part 42' by '-1'. A series of operation is executed until the number of transfer words in the command register is turned to zero.
申请公布号 JPS61128352(A) 申请公布日期 1986.06.16
申请号 JP19840250754 申请日期 1984.11.28
申请人 FUJI FACOM CORP 发明人 TAKEZOE FUMIHIKO
分类号 G06F13/12;G06F13/28;(IPC1-7):G06F13/12 主分类号 G06F13/12
代理机构 代理人
主权项
地址