发明名称 SISTEMA DE LOCALIZACION DE FALLOS PARA COMPROBAR LA VIABILIDAD DE COMPONENTES SITUADOS EN UNA PLACA DE CIRCUITO IMPRESO.
摘要 An in-circuit testing apparatus (manufacturing defects analyzer) for the determination of manufacturing defects in an electrical circuit board such as short circuits, tracking faults, mininserted omitted and out-of tolerance components etc., and not for effecting full functional testing of the circuit board, comprises an array of bidirectionally current conducting analog switching networks each of which defines a test point for connection to a node of a circuit board and connectable, under software control of the respective switchng network, either to a stimulus source or to a reference (e.g. ground) potential and simultaneously also to an input of a measurement facility. A resistor, capacitor, inductor or other circuit component can be connected between the test points defined by two of the switching networks and can thus be subjected to an appropriate stimulus and its response measured and analyzed for determining the viability of the respective component. A modified form of the apparatus enables the gain of discrete transistors also to be monitored. A desk-top form of the apparatus has a recess in its main housing for receiving an interchangeable board-probing module which is customized to a particular board to be tested and has a customized probe array coupled to one part of a universal interface connector, the other part of the universal interface connector being provided in the recess in the main housing such that the two parts come together when the module is inserted into the housing recess.
申请公布号 ES542237(D0) 申请公布日期 1986.06.16
申请号 ES19370005422 申请日期 1985.04.15
申请人 MARS INCORPORATED 发明人
分类号 G01R31/26;G01R31/319;G06F11/26;G06F11/277;(IPC1-7):G01R31/28 主分类号 G01R31/26
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