| 摘要 |
<p>PURPOSE:To reduce power consumption and to save number of external terminals and externally mounted components by using a PLL circuit taking a low frequency signal as a reference frequency signal so as to form a high frequency signal thereby generating a clock signal in a high frequency for the information processing. CONSTITUTION:An output of an oscillation circuit OSC is utilized as a reference frequency signal of a PLL circuit constituting a clock generating circuit CPG. That is, the oscillated output is fed to a phase comparator circuit PD via a NOR gate circuit G1 and an output of an oscillation circuit VCO whose frequency is divided by a prescaler PSC is fed to the circuit PD. An output signal of the circuit PD controls the VCO via an LPF. The oscillation frequency of the VCO is phase-locked at a high frequency to the reference frequency of the OSC in the PLL loop. In order to save power consumption of the circuit CPG, the operation of the PLL circuit is made intermittent. Thus, the positive feedback loop of the VCO is cut off by the output of a gate circuit G2. Further, the supply of the reference frequency signal to the circuit PD is controlled selectively by using the circuits G2, G1.</p> |
