| 摘要 |
PURPOSE:To cope with the change of a jitter by extracting a variable reproducing clock in accordance with the phase of the tape data and feeding back to a sampling part and a phase delaying part, in the circuit to sample a reproducing signal and extract the data and a clock. CONSTITUTION:In a reproducing signal (a), a phase interval value (e) at the sampling point of the reproducing signal (a) is calculated through an A/D con verter and a K bit parallel delaying circuit 2 at a calculating circuit 5. A signal (e) is compared with an output signal (g) of a (m) bit parallel delaying circuit 8, a numeric value is corrected by a coefficient K of a coefficient multiplier 10, added to a signal (g) by an adder 7 and correcting phase data (f) are added to the circuit 8. A binary code (m) bit of f is decoded to 2<m> bits, converted to a value on a time base by a P/S register, and a reproducing clock phi11 to correct a phase dislocation from a sampling pulse phi10 is extracted. A phi11 is fed back to the A/D converter 1, the circuit 2 and the circuit 8, added to an FF13 and reproducing data D0 can be obtained from the output of the FF13 synchronizing with phi11. |
