| 摘要 |
PURPOSE:To increase the drive power with less power consumption by using a tri-level type circuit comprising a CMOS recognizing three different input logical states. CONSTITUTION:When a level of an input terminal 1 is VDD (logical 1 level), an output of an inverter 12 is at VSS (logical 1' level), then an output of an inverter 10 is at VDD and an output of a 2-input NOR11 at a GND (logical 0 level). Then when the input terminal 1 is at GND, the output of the inverter 12 is at VSS and then the output of the inverter 10 is at VDD and the output of a 2-input NO11 is at VDD. Further, the input terminal 1 is at VSS, the output of the inverter 12 is at VDD and then the output of the inverter 10 and the 2-input NOR11 is both at GND. Thus, the combination of different binary output signals is outputted to the output terminals 2, 3 as shown in truth table 1 and three input levels at the input terminal 1 are recognized.
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