| 摘要 |
PURPOSE:To enhance the performance and the reliability by applying a turn ON voltage to a junction formed with a source of a MOS field effect transistor in a well region in response to the abnormal potential variation of the well region, thereby preventing a latchup phenomenon. CONSTITUTION:A semiconductor device inputs the rising voltage of a P-well region 2 through a P<+> ohmic contacting region 11 to a CMOS inverter for forming source voltage control means 12, amplifies the turn ON voltage of the same phase, and applies to the junction of an N<+> type source region 7. Accordingly, the conversion toward the forward direction of a P-N junction between the regions 7 and 2 is effectively stopped to prevent a latchup phenomenon peculiar for the CMOS, thereby avoiding the burnout due to an abnormal current. In this case, similar voltage rise occurs in the P-well region 2' of the CMOS inverter, but since latchup preventing means is provided in the CMOS structure, the turn OF voltage generating function is not disturbed. All can be formed of common CMOS structure, and a short channel can be performed without complicating the semiconductor manufacturing steps. |
