发明名称 DATA TRANSFER SYSTEM
摘要 PURPOSE:To improve the response characteristic to the 1st transfer request signal by forecasting the type of information which is to be transmitted next from the flow of operation on an interface so as to complete the corresponding setup. CONSTITUTION:A microprocessor of a master side device 1 forecasts the kind (I/O, C/D, MSG) of transmission information from a slave side device 2 to the device 1 depending on the operation flow on the interface between the devices 1 and 2, sets the result to a register 10 and sets up number of transfer bytes, transfer mode and memory address corresponding to the kind of information. When a transfer request signal REQ is transmitted from the device 2 in this state, the type information of transfer information from a register 10 by acomparator 11, and when the both are coincident, an acknowledgement signal ACK is transmitted to the device 2.
申请公布号 JPS61123243(A) 申请公布日期 1986.06.11
申请号 JP19840243985 申请日期 1984.11.19
申请人 FUJITSU LTD 发明人 SUGAYA SEIICHI
分类号 H04L29/08;H04L13/00 主分类号 H04L29/08
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