| 摘要 |
<p>A gate array integrated circuit incorporating memories which can realize various bit/word constitutions according to a customer's requirements, and a production method therefor. The gate array integrated circuit of the present invention provides a basic cell array region (1) in which a plurality of basic cells (2) are arranged, a memory cell matrix region (11a, 11 b) in which a plurality of memory cells (MC) are arranged, and a plurality of peripheral circuits which include address input circuits (15a, 15b) and decoders (14a, 14b) to access the memory cells. The memory cell matrix region may be divided according to a customer's requirement to form two or more independent memories (Ma, Mb) each having an address input circuit and a decoder.</p> |
