| 摘要 |
A first 5-stage ring counter generates a signal having a frequency of (4/5)fSC by dividing a frequency 8fSC of a signal. A second 5-stage ring counter generates a signal having a frequency of (4/5)fSC by dividing a frequency of a signal obtained by inverting the signal of frequency 8fSC by an inverter. A first sampling pulse output circuit generates a first sampling pulse from an output signal from the first 5-stage ring counter. A second sampling pulse output circuit generates a second sampling pulse from an output signal from the second 5-stage ring counter. A phase correction circuit causes synchronization of the count operation of the first 5-stage ring counter with a clock run-in signal. This phase correction is performed by shifting the phase of the output from the first 5-stage ring counter in units of the period of the signal of frequency 8fSC. When this phase correction is completed, the output signal from the first 5-stage ring counter is synchronized with the clock run-in signal such that the output signal is delayed by between 0 and 35 nsec with respect to the phase of the clock run-in signal. A discrininator divides a range of 0 to 35 nsec into two discrimination periods of 17.5 nsec each. The discriminator then discriminates during which one of the two discrimination periods the output signal from the first 5-stage ring counter appears. The discriminator then controls a sampling pulse switching circuit in accordance with the discrimination result.
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