| 摘要 |
<p>PURPOSE:To eliminate the waiting time of bit line for the recovery of potential and to reduce the access time by using the two bit lines alternatively which belong to the same row. CONSTITUTION:The 1st and 2nd prepositional amplifier 12, 13, OFF 15, AND gate 16, control switch 20, 21 consist of the switching means which switches use condition of the 1st and 2nd bit lines 3, 4 alternatively at every time when the row concerned is addressed. When the corresponding row and line address signal is supplied to select the 2nd memory cell 2, a DFF 15 reverses and the 1st prepositional amplifier 12 and control switch 20 is turned to active condition, and a low level output appears at the 1st bit line 3, and the output amplifier 14 has a low level output. While the 2nd memory cell is accessing, the 2nd bit line 4 is in non-use condition, and even if the same row is selected immediately continuously, the low level output of the memory cell immediately appears to the 2nd bit line 4 which is to be activated at that time.</p> |
