PHASE DIVISION PROCESSING SYSTEM

摘要

PURPOSE:To cope with an external device having a high speed by connecting in parallel plural pieces of CPU having a prescribed machine cycle and processing input/output data in a cycle equal to the value obtained by multiplying the machine cycle by the number of connected CPUs. CONSTITUTION:The clocks obtained by dividing with shifts of phases the reference clock given from a CPU clock generator 8 are supplied to CPU1-4 which are connected in parallel and work in the same clock cycle of a system. Each of the CPU1-4 is connected to a direction data selector 5 via a CPUI/O interface parts 11-41. While an input/output circuit consisting of a P/S converter 6 and an S/P converter 7 connected to the external devices are connected to the selector 5. Then the timing signals given from interface parts 11-31 are supplied to the selector 5 via the output and input side timing generators 51 and 52. The selector 5 switches the input and output circuits by means of the timing signals of CPU1-4. Thus it is possible to cope with the data processing of a high-speed external device.