发明名称 HIGH SPEED DPCM CIRCUIT
摘要 PURPOSE:To improve the operating speed to obtain a forecast signal from a critical pulse by the delay of a multiplier by providing a quantizer having the 2nd output outputted while being being multiplied with a forecast coefficient after quantization and the 1st output generating a quantized DPCM signal to the output of the 2nd delay element of a high speed DPCM circuit. CONSTITUTION:One output of the 1st delay element FF 7 is an input to the 1st adder via a multiplier 12. Then one output of the 1st adder 5 is fed to a flip-flop FF 7 acting like the 1st delay element. The other output of the 1st delay element FF 7 is multiplied with a forecast coefficient pXp at the 2nd multiplier 11. The output of the 2nd multiplier 11 is the 3rd input to a 3-input/2-output D/D converter 1. Two outputs are obtained from a PCM signal inputted as the 1st input and the 2nd, 3rd input signals in the 3-input/2-output D/D converter 1, and the outputs are added in the 2nd adder. The output of the 2nd adder 2 is fed to a quantizer 10 via a flip-flop 3 acting like the 2nd delay element.
申请公布号 JPS61121619(A) 申请公布日期 1986.06.09
申请号 JP19840242456 申请日期 1984.11.19
申请人 FUJITSU LTD 发明人 OKAZAKI TAKESHI;TSUDA TOSHITAKA;MATSUDA KIICHI
分类号 H03M7/32;H03M7/38;H04B14/06 主分类号 H03M7/32
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