| 摘要 |
PURPOSE:To prevent increase in the hardware scale by using a clock obtained by a differentiation circuit and a counter to sample and hold the first half bit data of a CMI code signal in the 1st flip-flop and obtaining a signal subject to NRZ conversion from an EOR gate. CONSTITUTION:When an original data DT at the transmission side is 010, the original data DT becomes a CMI code signal SCM1 of 010001 according to the CMI coding rules. The 1st flip-flop 11 receiving the SCM1 as the D input uses the 1st clock CKi fed to the clock input CK to sample and hold the SCM1. The CMI code signal SCM1 subject to sample and hold is exclusively ORed with the SCM1 appearing at the next at an EOR gate 13, and the signal SMRZ of the NRZ code form is obtained at the output of the EOR gate 13. A decoded signal S'CM1 is obtained by applying sample and hold to the signal SMRZ at the 2nd flip-flop 12 synchronously with the 2nd clock CK2.
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