| 摘要 |
PURPOSE:To avoid the collision of access to a shared memory between two processors at the master and slave sides respectively, by securing the synchroni zation between both processors in a mutually inverted state and therefore secur ing a state where one of both processors uses no bus while the other processor is using the bus. CONSTITUTION:The clock signals given from an oscillation circuit 8 are supplied to both processors 1 and 2 at the master and slave sides respectively. Then action clock signals ME and SE of both processors are supplied to an instruction cycle synchronizing circuit 7. The circuit 7 secures the synchronization between both signals ME and SE in a mutually inverted state of them, and memory ready signals MMR and SMR are supplied to processors 1 and 2 respectively. While a bus switch circuit 4 is connected to both processors, and the circuit 4 performs the switching connections among address buses 9 and 10 of processors 1 and 2 as well as data buses 12 and 13 and a shared memory 3. Thus one of both processors does not use the bus while the other processor is using the bus. This can avoid the collision of accesses to the memory 3. |
