发明名称 MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To enhance withstanding voltage for electrostatic breakdown and to reduce processes, in a IC comprising MISFETs, by constituting the peripheral part by the MISFET having a single drain structure, constituting the inner IC by the MISFET having a double-drain structure, and sharing a part of the manufacturing processes. CONSTITUTION:An n<-> type well region 2 is formed in a p<-> type Si substrate 1. Thick field insulating films 3 are provided on a P type channel stopper region 4. A thin insulating film 5 is deposited on the exposed part of the region 4. A gate electrode 6C is formed at the center of the surface. Thus a single-drain structured MISFET is obtained. The surface is covered by a mask 13. A double- drain structured MISFET is provided at the neighboring position. At this time one insulating film 3 is shared. A gate electrode 6B is formed between and said insulating film 3 the other facing insulating film 5. Thereafter, the source and drain regions of an n<-> type layer 7B are formed on both sides of the electrode 6B on n<+> type layer 8B. On the well region 2, p<+> type source and drain regions 9C are formed.
申请公布号 JPS61120459(A) 申请公布日期 1986.06.07
申请号 JP19840240619 申请日期 1984.11.16
申请人 HITACHI LTD 发明人 SHIBATA TAKASHI
分类号 H01L27/092;H01L21/265;H01L21/8238;H01L21/8246;H01L27/088;H01L27/10;H01L27/112;H01L29/78 主分类号 H01L27/092
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