| 摘要 |
PURPOSE:To reduce the size of an address decoder circuit by using transistors (TR) to which common address signals are inputted in common, and connecting remaining TRs of respective address decoders to said TRs in parallel and constituting plural address decoders. CONSTITUTION:An address decoder 20 which selects a word line W0 when address signals A0, A1, A2, and A3 are all at a high level and an address decoder 21 which selects a word line W1 when the address signals A0, A1, A2, and A3 are all at the high level share the n channel TRs T3, T4, and T5 to which those common address signals A1, A2, and A3 are inputted at their gates. Other TRs of the address decoders 20 and other TRs of the address decoder 21 are connected in parallel to the series circuit of those shared TRs T3 T4, and T5, and the address decoders 20 and 21 constitute one unit. |
