| 摘要 |
PURPOSE:To implement high speed operation, by providing a double-base structure of cluster transistors constituting a logic gate circuit, and providing the minimum size for an N<+> embedded collector layer. CONSTITUTION:Three input cluster transistors Q11-Q13 have pairs of base taking out layers B11 and B12, B21 and B22, and B31 and B32 on both sides of emitters E1-E3. Thus the base resistances are lowered. The emitters E1-E3 and the base taking out layers B11, B12-B31 and B32 are arranged in a straight line. Common collector taking out layers C12 and C23 for the element Q11 and Q12 and Q12 and Q13 are arranged between B12 and B21 and between B22 and B31. An N<+> embedded collector (broken line) layer including the B layers, the E layers and the collector taking out layers C12 and C23 is formed. Then the area of the collector layers becomes minimum. The connecting capacity between the collector substrates becomes minimum. The operating speed and a gain band product f1 are improved. Specified Al wirings L1-L6 are further provided. The wirings L4 and L5 and the wiring L6, whose one end is connected to a load resistance, are connected by low resistance poly SiP. Then the wiring design becomes easy. |
