发明名称 HIGH-WITHSTANDING-VOLTAGE SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To prevent the concentration of the surface electric field at the interface of an oxide film and to obtain a compact, high withstanding voltage IC, by bending the edge of a depletion layer on the low concentration side to the side of an IC substrate in the IC having a planar structure, and forming the thick oxide film on the depletion layer region. CONSTITUTION:When the potential of a wiring metal 1 on the high concentration side at a P-N junction 5 is lower than that of a wiring 2 on the lower concentration side, a depletion layer 6 is yielded. Before the depletion layer 6 reaches a planar surface, the layer 6 reaches an oxide film 4, which is formed so as to form an obtuse angle with the depletion layer 6, at the lower side from the surface and at the side of a substrate 8. The layer 6 is bent to the substrate 8 at the interface of the film 4. The surface electric field of the oxide film interface 4 is alleviated. The oxide film 4 is formed so as to form an acute angle with a surface 7 on the upper side of the surface 7. Therefore, the distance between the substrate 8 and the wiring metal 1 becomes large. The concentration of the electric field at the tip of the wiring 1 is alleviated by only extending the wiring 1 to the region of the oxide film 4. In this constitution, the high withstanding voltage IC with small sizes can be obtained.
申请公布号 JPS61120448(A) 申请公布日期 1986.06.07
申请号 JP19840242114 申请日期 1984.11.16
申请人 NEC CORP 发明人 YAMAMURA SHIGEHARU
分类号 H01L21/768;H01L23/522;(IPC1-7):H01L21/88 主分类号 H01L21/768
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