| 摘要 |
PURPOSE:To omit an address counter and to reduce the chip size by applying a clock pulse directly to a shift register for selection of an address. CONSTITUTION:The output of an NAND gate 14 is applied to a shift register 12 for selection of columns as a shift clock. While a blanking pulse is applied to a shift register 12 for selection of columns from an input terminal 111. Then the output of an NAND gate 15 is applied to a shift register 13 for selection of rows as a shift clock. While a blanking pulse is applied to the register 13 from the terminal 111. The output of the register 12 is applied to a sense amplifier 17, and the columns of a memory cell array 11 are selected successively. While the rows of the array 11 are selected successively by the output of the register 13.
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