发明名称 PROCESSOR CONTROL SYSTEM
摘要 PURPOSE:To design the software without calculating an accurate processing time by completing the software in the almost roughly estimated time so that the processing is through within a real time processing cycle and finally designating a halt instruction. CONSTITUTION:The output of a basic oscillation circuit is supplied through a terminal (a) and divided by a dividing circuit 1. A synchronizing clock which rises up every real time processing cycle is supplied through a clock terminal (b) and differentiated by a differentiating circuit 2 to set a flip-flop 4. Then an AND circuit 5 sends the clocks divided by the circuit 1 to a processor 6. The processor 6 carries out each processing operation and resets the flip-flop 4 when a halt instruction execution detecting circuit 6 detects the halt execution. Thus the supply of clocks is stopped to the processor 6. The processor 6 stops its working for a period when the flip-flop 4 is kept reset owing to the discontinuation of a primary clock.
申请公布号 JPS61118839(A) 申请公布日期 1986.06.06
申请号 JP19840240121 申请日期 1984.11.14
申请人 FUJITSU LTD 发明人 ENDO CHIHIRO
分类号 G06F9/30;G06F9/06 主分类号 G06F9/30
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