发明名称 |
INTERRUPTION TEST SYSTEM OF PROCESSOR |
摘要 |
PURPOSE:To improve the test quality by producing both plural same levels and the interruption signals having level differences at a time and causing the conflict of channels. CONSTITUTION:Terminals (a) and (b) of a processor 1 have high and low interruption levels. When a test device 2 is started, the value of an interruption interval register 3 is set to a down-counter 4. This set value is counted down. Then an interruption signal generating circuit 5 and a channel discrimination data register 6 are driven when the down-count value reaches zero. The channel number is sent to the processor 1 from the register 6 through a bus 8. Then test devices 2 and 2' send '1' to the terminal (a) through an OR circuit 7. While a test device 2'' sends '1' and the channel number to the terminal (b) through the bus 8 to produce the conflict of the channel. Thus a discrimination test is given to the processor 1. |
申请公布号 |
JPS61118843(A) |
申请公布日期 |
1986.06.06 |
申请号 |
JP19840240111 |
申请日期 |
1984.11.14 |
申请人 |
FUJITSU LTD |
发明人 |
NISHIMURA NAOYUKI;HASHIMOTO SHIGERU |
分类号 |
G06F9/46;G06F9/48;G06F11/22;G06F11/28 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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