| 摘要 |
PURPOSE:To avoid malfunction by using the 1st-4th F flip-flops to count from 1 to 9, using the 5th D flip-flop to count the tens digit, and combining them to count repetitively the count from 1 to 12. CONSTITUTION:An output Q5 is logical 1 for the tens digit of the count, resulting that the level is logical 1 when the count is 10, 11 and 12. The units digit is represented by the combination of outputs Q1-Q4. Then the Q1 is logical 1 when the count is an odd number, the Q2is logical 1 when the count is 2, 3, 6, 7 and 12, the Q3 is loginal 1 when the count is 4, 5, 6, 7 and the Q4 is logical 1 when the count is 8, 9. The counter circuit restores to loginal 1 after the counte reaches 12. A clock signal CK is fed directly to the D flip-flops 1-5 (as required via an inverter only) and a value of data inputted to each D flip-flop is decided based on the said clock signal.
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