发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To execute the picture generation processing at a high speed by providing three or more operators, register files whose number is equal to the number of these operators, and a data transfer means which can substitute data between each operator and each register file. CONSTITUTION:Each of register files 40-42 consists of a high-speed memory element and is constituted of two, front and rear faces of a front register file 40' and a rear register file 40''. The front face holes data which operators 20-22 process, and the rear face transmits data to and receives data from a main memory. When the processing of data on the front face is terminated and data to be next processed is prepared on the rear face, front and rear register files are switched. A data transfer means 30 consists of selectors SEL, and the register file whose data should be selected is determined by a selector control signal S2. Various resources such as arithmetic and logic units ALU, multiplying units MPY, etc. are controlled by the same control line, and operators perform the same operation. Signals for said control are given from a control means omitted in the figure.
申请公布号 JPS61117665(A) 申请公布日期 1986.06.05
申请号 JP19840237650 申请日期 1984.11.13
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 NARUSE TADASHI;YOSHIDA MASAHARU;KANEKO HIROSHI;TAKAHASHI TOKIICHIROU
分类号 G06F15/16;G06F15/80;G06F17/10;G06T15/80 主分类号 G06F15/16
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