| 摘要 |
PURPOSE:To eliminate disturbance of synchronization of an output clock signal when synchronization is finished by using a phase shift device to convert a return clock signal inputted to a phase comparator into a signal added with a phase shift caused at every other pulse. CONSTITUTION:An input data signal S1 and a return clock signal S6 are inputted to the phase comparator 1. The phase comparator 1 detects a phase difference between the S1 and S6, and when the phase of the S6 is led to the S1, a pulse signal having a pulse width proportional to the phase difference is outputted as a lead phase difference signal S2. When the S6 is lagged to the S1, a pulse signal having a pulse width proportional to the phase difference is outputted as a lag phase difference signal S3. The S2 or S3 is inputted to a filter 2, which inverts the S2 and synthesize in with the S3 and a controlled voltage signal from which a high frequency component is eliminated is outputted to the voltage controlled oscillator 3. The voltage controlled oscillator 3 is oscillated in a frequency proportional to the S4 and outputs an output clock signal S5. The S5 is branched and inputted to the phase shift device, from which the return clock signal S6 is outputted.
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